1. Field of the Invention
The present disclosure relates to a semiconductor device, and more particularly, to a data receiver which uses a folded differential voltage sampler operating in synchronization with a clock signal and can detect data in a differential signal manner by receiving a data line and differential reference signals, and a method for receiving data.
2. Description of the Related Art
Methods for transmitting and receiving data to and from a semiconductor device at high speed include a method for differentially transmitting and receiving. This method, however, requires many data lines or data input/output pins.
FIG. 1A is a block diagram of a conventional data receiver using a single reference signal. FIG. 1B is a timing diagram illustrating the waveforms of signal lines shown in FIG. 1. Referring to FIGS. 1A and 1B, a data receiver 10 includes a single reference signal line 1, through which a reference signal VREF is received, and N data lines 3, 5, . . . , 7, through which N data signals DATA1, DATA2, . . . , DATAN are received. The data receiver 10 compares the reference VREF with each of N data DATA1, DATA2, . . . , DATAN and detects the received data DATA1, DATA2, . . . , DATAN.
However, since the data receiver 10 uses a single reference signal, it is sensitive to noise and thus has difficulty receiving data at high speed. In addition, as the transmission of data becomes faster, the level of data becomes smaller due to an attenuation effect of transmission lines. Accordingly, the difference DD1 in voltage between the reference signal VREF and a data signal DATAi continues to decrease, making it more difficult for the data receiver 10 to precisely detect the data signal DATAi.
FIG. 2A is a block diagram of a conventional receiver using a differential signal. FIG. 2B is a timing diagram illustrating the waveforms of data lines shown in FIG. 2A. Referring to FIGS. 2A and 2B, a receiver 20 using a differential signal includes 2N data lines 11, 13, . . . , 15, 17, through which 2N data signals DATA1, /DATA1, . . . , DATAN,/DATAN are received. Here, the data signals DATA1 and /DATA1 are complementary signals.
In the case of the data receiver 20, the difference DD2 in voltage between a data signal DATAi and its complementary data signal /DATAi can be equal to the voltage difference DD1 in a single reference signal receiver 10. Thus, it is possible to decrease the swing width of the data signal DATAi and the power consumption of the data receiver 20 and thus receive data at high speed. However, the data receiver 20 needs twice as many data lines than the data receiver 10 adopting a single reference signal.
In the case of a data receiver disclosed in U.S. Pat. No. 6,160,423, ('423) the trip point of two inverters may vary according to variations in process, voltage, and temperature, and thus it is impossible to precisely detect data input into the data receiver. In addition, when the output levels of comparators are very low, the data receiver cannot precisely detect data.
When the data receiver disclosed in the '423 patent operates at a high frequency, it cannot precisely detect data, and glitches may occur during the operation of switches. Finally, since the data receiver disclosed in the '423 patent uses exclusive OR (XOR) logic gates, the layout area of the data receiver is increased.